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NXP Semiconductors /LPC15xx /ACMP /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (ACMP1_ACMP0)ROSCCTL 0 (INTERNAL)EXT_RESET 0RESERVED

EXT_RESET=INTERNAL, ROSCCTL=ACMP1_ACMP0

Description

Comparator block control register

Fields

RESERVED

Reserved.
ROSCCTL

Selects the which comparators set and reset the ROSC output.

0 (ACMP1_ACMP0): ACMP1/ACMP0. The ROSC output is set by ACMP1 and reset by ACMP0.

1 (ACMP0_ACMP1): ACMP0/ACMP1. The ROSC output is set by ACMP0 and reset by ACMP1.
EXT_RESET

Selects the reset source for the ROSC output.

0 (INTERNAL): Internal. The ROSC output is reset by the internal chip reset.

1 (FROM_PIN_ROSC_RESET): From pin ROSC_RESET. The ROSC output is reset by the ROSC_RESET input.
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data